1. Field of the Invention
This invention relates to semiconductor device manufacturing, and more particularly, to improved methods for processing a semiconductor topography having a substantially planar upper surface.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Fabrication of an integrated circuit involves numerous processing steps. After implant regions (e.g., source/drain regions) have been placed within a semiconductor substrate and gate areas defined upon the substrate, an interlevel dielectric is formed across the topography to isolate the gate areas and the implant regions from overlying conducting regions. Interconnect routing is then placed over the interlevel dielectric and connected to the implant regions and/or the gate areas by ohmic contacts formed through the interlevel dielectric. Alternating levels of interlevel dielectric and interconnect may be placed across the semiconductor topography to form a multi-level integrated circuit.
Forming substantially planar upper surfaces of a semiconductor topography during intermediate process steps may facilitate fabrication of layers and structures that meet design specifications. For example, a dielectric layer may be formed across a previously patterned layer of a semiconductor topography using a process such as chemical vapor deposition (“CVD”). Elevational disparities of the deposited dielectric layer may be reduced by planarizing the deposited dielectric layer using a process such as chemical mechanical polishing (“CMP”). A contact opening may be formed within the planarized dielectric layer and subsequently filled with a layer of conductive material. In this manner, the layer of conductive material may be formed within the contact opening and on an upper surface of the planarized dielectric layer. As such, the layer of conductive material may also be planarized such that an upper surface of the contact structure may be substantially planar with an upper surface of the dielectric layer.
Additional layers and structures may be formed upon the contact structures and the dielectric layer. The additional layers and structures may include, for example, additional dielectric layers, additional contact structures, local interconnect wires, and/or metallization layers. In this manner, the planarized upper surface of the contact structures and the dielectric layer may facilitate the formation of such additional layers and structures having uniform vertical and lateral dimensions. For example, the planarization of the semiconductor topography may facilitate the formation of local interconnect structures having a substantially uniform thickness by providing a planar surface upon which a dielectric material may be deposited to insulate adjacent local interconnect structures. Moreover, the planarization of the semiconductor topography may aid in forming local interconnect structures having uniform lateral dimension by providing a planar surface upon which a patterned masking layer may be formed. In this manner, a masking layer may be accurately patterned by a lithography technique such that the pattern may be accurately transferred to a dielectric layer to form local interconnect structures. Accordingly, layers and structures of a semiconductor device may be formed having dimensions which are approximately equal to design specifications for the semiconductor device.
Forming a substantially planar upper surface of such layers and structures may play an important role in the functionality of a semiconductor device. For example, problems with step coverage may arise when a dielectric, conductive, or semiconductive material is deposited over a topological surface having elevationally raised and recessed regions. Step coverage is defined as a measure of how well a film conforms over an underlying step and is expressed by the ratio of the minimum thickness of a film as it crosses a step to the nominal thickness of the film over horizontal regions. Furthermore, substantially planar surfaces may become increasingly important as the feature sizes of semiconductor devices are reduced, since the depth of focus required to pattern an upper surface of a semiconductor topography may increase with reductions in feature size. If a topography is nonplanar, the patterned image may be distorted and the intended structure may not be formed to the specifications of the device. Furthermore, correctly patterning layers upon a topological surface containing fluctuations in elevation may be difficult using optical lithography. The depth-of-focus of the lithography alignment system may vary depending upon whether the resist resides in an elevational “hill” or “valley” area. The presence of such elevational disparities therefore makes it difficult to print high-resolution features.
As mentioned above, CMP is a technique commonly employed to planarize or remove the elevational fluctuations in the surface of a semiconductor topography. A conventional CMP process may involve placing a semiconductor wafer facedown on a polishing pad, which lies on or is attached to a rotatable table or platen. A typical polishing pad medium may include polyurethane or polyurethane-impregnated polyester felts. During the CMP process, the polishing pad and the semiconductor wafer may be rotated relative to each other as the wafer is forced against the pad. An abrasive, fluid-based chemical suspension, often referred to as a “slurry,” may be deposited onto the surface of the polishing pad. The slurry fills the space between the polishing pad and the wafer surface such that a chemical in the slurry may react with the surface material being polished. The rotational movement of the polishing pad relative to the wafer causes abrasive particles entrained within the slurry to physically strip the reacted surface material from the wafer. Alternatively, a liquid substantially free of particulate matter may be deposited onto the polishing pad during polishing. In addition, the pad itself may physically remove some material from the surface of the semiconductor topography. Therefore, the process may employ a combination of chemical stripping and mechanical polishing to form a planarized surface.
Unfortunately, a CMP process may not form a substantially planar surface across an entire semiconductor topography. For example, if the polishing rate of CMP varies across a topography, a planarized semiconductor topography may have substantial elevational disparities. Such disparities may be particularly prevalent at an edge of the topography. For example, a thickness of a semiconductor topography may be greater at the edge of the topography than at an inner portion of the topography. The greater thickness of the semiconductor topography at its edge may be due to a slow polish rate at the edge of the topography as compared to polish rates at other regions of the topography. Several factors may influence the polish rates of a CMP process. For example, the polish rates may depend on the pressure used to force the semiconductor topography against a polishing pad during CMP. The pressure may be greater near the inner portion of the wafer than at the edge of the wafer. In fact, the edge of the semiconductor topography may not contact the pad due to pad distortions that may occur from the pressure used to force the topography against the pad. In this manner, the outer portions of the semiconductor topography may not be polished at the same rate as inner portions of the semiconductor topography. Additional factors which may affect polish rates of the CMP process may include the polishing tool, the pad materials, the slurry, the surface materials being polished, and the rotational and lateral movement of the polishing pad relative to the semiconductor topography.
Elevational disparities which may be present on a semiconductor topography subsequent to chemical mechanical polishing may inhibit the formation of semiconductor devices on a portion of the semiconductor topography. For example, a thickness of the semiconductor topography may be greater at an outer edge of the semiconductor topography than at an inner portion of the semiconductor topography. As such, the thickness of the semiconductor topography at the outer edge may be outside of design specifications for a semiconductor device. Consequently, semiconductor devices formed at the outer edge of such a semiconductor topography may have dimensions which deviate significantly from design specifications. In this manner, acceptable devices may not be formed on an area of the semiconductor topography having such elevational disparities, thereby reducing the number of devices which may be formed on the semiconductor topography. As such, the presence of such elevational disparities on a semiconductor topography may reduce manufacturing yield and may increase production costs per semiconductor device.
Accordingly, it would be advantageous to develop a method for forming a semiconductor topography having a substantially planar upper surface across substantially the entire semiconductor topography including its outer edge.